Problems arise in making electrical connection to electronic semiconductor devices having a plurality of connection pins. Modern semiconductor chips and packages frequently have a high pin count as well as a requirement for low inductance in the electrical connections that are made to the pins. Semiconductor chips and packages have commonly been provided with a plurality of peripheral projecting conducting tabs to which external circuitry has been connected by soldering. Such projecting tabs have increased the path length and thereby inductance of the connections and this has led to extensive use of chips or packages in which the external contact points are provided by projecting bumps of soft conducting material. Such devices are already known as bumped grid arrays and include solder grid arrays, ball grid arrays and bumped chips. Such conducting bumps usually comprise a plurality of rows forming an array on one or more faces of the chip or package and are not formed as peripheral extensions of the package. When using such chips or packages on a printed circuit board it is impractical to make interconnections between two bumps across the face of the device as conductors would need to be routed around neighbouring bumps. Usually the connections will be made through conductors on a printed circuit board so that the interconnection is routed through conductors at one or more layers on the printed circuit board and thereby avoiding obstructions. Problems can arise in using reflow solder to connect such chips or packages onto a circuit board. The elevated temperatures used may damage the components or cause mechanical stresses to be induced that may cause premature system failure. Furthermore some components may need to be replaced.
It is an object of the present invention to provide an improved connection in an electrical assembly avoiding the use of reflow solder.